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a
FEATURES Low Cost Low Transition Noise between Code 12-Bit Accurate 1/2 LSB Nonlinearity Error over Temperature No Missing Codes at All Temperatures 10 s Conversion Time Internal or External Clock 8- or 16-Bit Data Bus Compatible Improved ESD Resistant Design Latchup Resistant Epi-CMOS Processing Low 95 mW Power Consumption Space-Saving 24-Lead 0.3" DIP, or 24-Lead SOIC APPLICATIONS Data Acquisition Systems DSP System Front End Process Control Systems Portable Instrumentation GENERAL DESCRIPTION
CMOS Microprocessor-Compatible 12-Bit A/D Converter ADC912A
FUNCTIONAL BLOCK DIAGRAM
AGND VREFIN 5k 12-BIT DAC AIN VDD VSS
ADC912A
SUCCESSIVE APPROXIMATION REGISTER
12-BIT LATCH 4 8 CONTROL LOGIC
BUSY CS RD HBEN
MULTIPLEXER 8 THREE-STATE OUTPUT DRIVERS THREE-STATE OUTPUT DRIVERS CLOCK OSCILLATOR
CLK OUT CLK IN
D11 D8
D7 D4 DGND D3/11 D0/8
The ADC912A is a monolithic 12-bit accurate CMOS A/D converter. It contains a complete successive-approximation A/D converter built with a high-accuracy D/A converter, a precision bipolar transistor high-speed comparator, and successiveapproximation logic including three-state bus interface for logic compatibility. The accuracy of the ADC912A results from the addition of precision bipolar transistors to Analog Devices' advanced-oxide isolated silicon-gate CMOS process. Particular attention was paid to the reduction of transition noise between adjacent codes achieving a 1/6 LSB uncertainty. The low noise design produces the same digital output for dc analog inputs
256
not located at a transition voltage, see Figures 1 and 2. NPN digital output transistors provide excellent bus interface timing, 125 ns access and bus disconnect time which results in faster data transfer without the need for wait states. An external 1.25 MHz clock provides a 10 s conversion time. In stand-alone applications an internal clock can be used with external crystal. An external negative five-volt reference sets the 0 V to 10 V input range. Plus 5 V and minus 12 V power supplies result in 95 mW of total power consumption.
NUMBER OF OCCURRENCES
192
128
64
DIGITAL OUTPUT
10 0%
256 SUCCESSIVE CONVERSIONS WITH AIN = 4.99756V
100 90
TRANSITION NOISE
0 2045 2046 2047 2048 2049 OUTPUT CODE - Decimal
ANALOG INPUT
Figure 1. Code Repetition
Figure 2. Transition Noise Cross Plot
REV. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2001
(VDD = +5 V 5%, VSS = -11.4 V to -15.75 V, VREFIN = -5 V, Analog Input O V to 10 V; External fCLK = 1.25 MHz; -40 C to +85 C applies to ADC912A/F unless otherwise noted.)
Parameter STATIC ACCURACY Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error Full-Scale Tempco1 ANALOG INPUT Input Voltage Range Input Current Range POWER SUPPLIES Positive Supply Current Negative Supply Current Power Consumption Power Supply Rejection Ratio DIGITAL INPUTS Logic Input High Voltage Logic Input Low Voltage Logic Input Current Digital Input Capacitance DIGITAL OUTPUTS Logic Input High Voltage Logic Input Low Voltage Three-State Output Leakage Digital Input Capacitance DYNAMIC PERFORMANCE Conversion Time Symbol INL DNL VZSE GFSE TCGFS VIN IIN IDD ISS PDISS PSRR+ PSRR- VINH VINL IIN CIN VOH VOL IOZ COUT TC VDD = +5 V2 VSS = -12 V2 VDD = +5 V2, VSS = -12 V2 VDD = 5%, AIN = 10 V VSS = 5%, AIN = 10 V CS, RD, HBEN CS, RD, HBEN CS, RD, HBEN Digital Inputs, CS, RD, HBEN, CLKIN ISOURCE = 0.2 mA ISINK = 1.6 mA D11-D0/8 D11-D0/81 fCLK = 1.25 MHz3 Synchronous Clock Asynchronous Clock 2.4 0.8 1 10 Conditions Min -1 -1 -5 -6 5 0 0 5 3 70 1/2 1/2 Typ Max +1 +1 +5 +6 15 10 3 7 5 95 4 4 Unit LSB LSB LSB LSB ppm/C V mA mA mA mW LSB LSB V V A pF V V A pF
ADC912A-SPECIFICATIONS
VDD = +5 V, VSS = -12 V VDD = +5 V, VSS = -12 V
7 4
8
0.4 10 15
10.4
10.4 11.2
s s
NOTES 1 Guaranteed by design. 2 Converter inactive; CS, RD = High, A IN = 10 V. 3 See Synchronizing Start Conversion information in Converter Operation Details. Typicals (typ) are median values measured at 25 C. See Typical Performance Characteristics for additional information. Specifications subject to change without notice.
5V 3k DBN 3k DGND A. HIGH-Z TO V OH (t3) AND VOL TO V OH (t6) CL DBN CL DGND B. HIGH-Z TO VOL (t3) AND V OH TO VOL (t6)
5V 3k DBN 3k DGND A. VOH TO HIGH-Z 10pF DBN 10pF DGND B. VOL TO HIGH-Z
Figure 3. Load Circuits for Access Time
Figure 4. Load Circuits for Output Float Delay
-2-
REV. B
ADC912A
(VDD = +5 V 5%, VSS = -11.4 V to -15.75 V, VREFIN = -5 V, Analog Input 0 V to 10 V; External fCLK = 1.25 MHz; -40 C to +85 C applies to ADC912A/F unless otherwise noted. See Figures 5 to 8.)
Parameter CS to RD Setup Time RD to BUSY Propagation Delay Data Access Time after READ Read Pulsewidth CS to RD Hold Time New Data Valid after BUSY Bus Disconnect Time HBEN to RD Setup Time HBEN to RD Hold Time Delay between Successive Read Operations Symbol t1 t2 t3 3 t4 3 t5 t6 3 t7 t8 t9 t10 Conditions Min 0 CL = 100 pF 90 0 CL = 100 pF 20 20 20 350 -30 60 0 90 65 150 125 Typ Max Unit ns ns ns ns ns ns ns ns ns ns
TIMING CHARACTERISTICS1, 2
250
NOTES 1 Guaranteed by design. 2 All input control signals are specified with t R = tF = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. 3 t3, t4, and t6 are measured with the load circuits of Figure 3 and timed for and output to cross 0.8 V or 2.4 V. 4 t7 is the time required for the data lines to change 0.5 V when loaded with the circuits of Figure 4. Specifications subject to change without notice.
CS
TIMING DIAGRAMS
CS
RD
t1
t5 t4 t2
t1 t4
t5
t1
RD
t5 t10 tCONV t6
OLD DATA DB11 - DB0 D10 D9 D8 D7
t1
BUSY
tCONV t7
OLD DATA DB11 - DB0
t2 t3
tCONV
t2
BUSY
t3
DATA
t7
NEW DATA DB11 - DB0
t3
DATA DATA D OUTPUTS 11
t7
NEW DATA DB11 - DB0 D6 D5 D4 D3/11 D2/10 D1/9 D0/8
DATA D OUTPUTS 11
D10
D9
D8
D7
D6
D5
D4
D3/11 D2/10 D1/9 D0/8
FIRST READ DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 (OLD DATA) SECOND DB DB DB DB DB DB DB DB DB DB DB DB 11 10 9 8 7 6 5 4 3 2 1 0 READ
READ DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Figure 5. Parallel Read Timing Diagram, Slow-Memory Mode (HBEN = LOW)
Figure 7. Parallel Read Timing Diagram, ROM Mode (HBEN = LOW)
HBEN
t8
HBEN
CS
t9
t8
t9
t8
t9
t8
CS
t9 t5 t10 t7 t6
OLD DATA DB7 - DB0 NEW DATA DB7 - DB0
t8
t9
RD
t1 t4 t2
BUSY
t5
t1 t4
t5
t1 t4 t10 t2
t5
t1
RD
t1 t4
t5
tCONV t3 t7
OLD DATA DB7 - DB0
t2
BUSY
tCONV
t3
t7
NEW DATA DB11 - DB8
t3
t7
NEW DATA DB7 - DB0
t3
DATA
t3
t7
DATA
NEW DATA DB11 - DB8 D3/11 DB3 DB11 D2/10 DB2 DB10 D1/9 DB1 DB9 D0/8 DB0 DB8
DATA OUTPUTS FIRST READ SECOND READ
D7 DB7 LOW
D6 DB6 LOW
D5 DB5 LOW
D4 DB4 LOW
DATA OUTPUTS FIRST READ (OLD DATA) SECOND READ THIRD READ
D7 DB7 LOW DB7
D6 DB6 LOW DB6
D5 DB5 LOW DB5
D4 DB4 LOW DB4
D3/11 DB3 DB11 DB3
D2/10 DB2 DB10 DB2
D1/9 DB1 DB9 DB1
D0/8 DB0 DB8 DB0
Figure 6. Two-Byte Read Timing Diagram, Slow-Memory Mode
Figure 8. Two-Byte Read Timing Diagram, ROM Mode
REV. B
-3-
ADC912A
ABSOLUTE MAXIMUM RATINGS
(TA = 25C, unless otherwise noted)
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V VSS to DGND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to -7 V VREFIN to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . VSS to VDD AGND to DGND . . . . . . . . . . . . . . . . -0.3 V to VDD + 0.3 V AIN to AGND . . . . . . . . . . . . . . . . . . . . . . . . -15 V to +15 V Digital Input Voltage to DGND, Pins 17, 19-21 . . . . . . . . . . . . . . . . . -0.3 V to VDD + 0.3 V Digital Output Voltage to DGND, Pins 4-11, 13-16, 18, 22 . . . . . . . . . -0.3 V to VDD + 0.3 V
Operating Temperature Range Extended Industrial: ADC912A/F . . . . . . . -40C to +85C Storage Temperature . . . . . . . . . . . . . . . . . . -65C to +150C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300C Maximum Junction Temperature (TJ max) . . . . . . . . . . 150C Package Power Dissipation . . . . . . . . . . . . . . (TJ max-TA)/JA Thermal Resistance JA Plastic DIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57C/W SOIC-24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70C
ORDERING GUIDE
Model ADC912AFP ADC912AFS
Temperature Range -40C to +85C -40C to +85C
INL (LSB) 1 1
Package Description 24-Lead Narrow-Body Plastic 24-Lead Wide-Body SOIC
Package Option N-24 R-24
Table I. Analog Input to Digital Output Code Conversion
Analog Input Voltage 0 V to 10 V -10 V to +10 V +FS - 1 LSB +FS - 1 1/2 LSB Midscale + 1/2 LSB Midscale -FS + 1/2 LSB -FS 9.9976 9.9964 5.0012 5.0000 0.0012 0.0000 9.99951 9.9927 0.0024 0.0000 -9.9976 -10.000
Output Code* DB11 (MSB) DB0 (LSB) 1111 1111 1111 1 1 1 1 1 1 1 1 1111 1000 0000 000 1000 0000 0000 0000 0000 000 0000 0000 0000
*The symbol"" indicates a 0 or 1 with equal probability.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADC912A features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
-4-
REV. B
ADC912A WAFER TEST LIMITS (@ V
Parameter Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error Analog Input Resistance Logic Input High Voltage Logic Input Low Voltage Logic Input Current Logic Output High Voltage Logic Output Low Voltage Positive Supply Current Negative Supply Current
DD
= +5 V, VSS = -12 V or -15 V, VREF = -5 V, AIN = 0 V to 10 V, and TA = 25 C, unless otherwise noted.)
Conditions ADC912AG Limit 1 1 8 8 4/6 2.4 0.8 1 4 0.4 7 5 Unit LSB max LSB max LSB max LSB max k min/max V min V max A max V min V max mA max mA max
Symbol INL DNL VZSE GFSE RAIN VINH VINL IIN VOH VOL IDD ISS
Guaranteed by Design CS, RD, HBEN CS, RD, HBEN CS, RD, HBEN ISOURCE = 0.2 mA ISINK = 1.6 mA VDD = +5 V, CS = RD = VDD, AIN = +10 V VSS = -12 V, CS = RD = VDD, AIN = +10 V
NOTE Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
10V C1 -5V C1
R + C2 R + C2
1 2 3 4 5 6 24 23
R C1 R + C2 + C2
+5V
-15V
C1 22 NC
21
R R
ADC912A
20
NC
7 8 9 10 11
TOP VIEW 19 (Not to Scale)
17
18 NC
R
16 NC 15 NC 14 NC 13 NC
R = 10 C1 = 0.01 F C2 = 4.7 F NC = NO CONNECT POWER SUPPLY SEQUENCE: +5V, -15V, -5V, +10V
12
Figure 9. Burn-In Circuit
REV. B
-5-
ADC912A
PIN FUNCTION DESCRIPTIONS Pin l 2 3 4 . . . 11 13 . . . 16 Mnemonic AIN VREFIN AGND D11 . . . D4 D3/11 . . . D0/8 Description Analog Input. 0 V to 10 V. Voltage Reference Input. Requires external -5 V reference. Analog Ground. Three-state data outputs become active when CS and RD are brought low. Individual pin function is dependent upon High Byte Enable (HBEN) input. DATA BUS OUTPUT, CS and RD = LOW
Pin 4 Mnemonic* HBEN = LOW HBEN = HIGH D11 DB11 DB11 Pin 5 D10 DB10 DB10 Pin 6 D9 DB9 DB9 Pin 7 D8 DB8 DB8 Pin 8 D7 DB7 Low Pin 9 D6 DB6 Low Pin 10 Pin 11 Pin 13 Pin 14 Pin 15 Pin 16 D5 DB5 Low D4 DB4 Low D3/11 DB3 DB11 D2/10 DB2 DB10 D1/9 DB1 DB9 D0/8 DB0 DB8
*D11 . . . D0/8 are the ADC data output pins. DB11 . . . DB0 are the 12-bit conversion results. DB11 is the MSB.
12
17 18 19
DGND CLK IN CLK OUT HBEN
20 21 22 23 24
RD CS BUSY VSS VDD
Digital Ground. Clock Input Pin. An external TTL-compatible clock may be applied to this pin. Alternatively a crystal or ceramic resonator may be connected between CLK IN (Pin 17) and CLK OUT (Pin 18). Clock Output Pin. An inverted CLK IN signal appears at CLK OUT when an external clock is used. See CLK IN (Pin 17) description for crystal (resonator). High Byte Enable Input. Its primary function is to multiplex the 12 bits of conversion data onto the lower D7 . . . D0/8 outputs (4 MSBs or 8 LSBs). See pin description 4 . . . 11 and 13 . . . 16. Also disables conversion start when HBEN is high. READ Input. This active LOW signal, in conjunction with CS, is used to enable the output data three state drivers and initiates a conversion if CS and HBEN are low. Chip Select Input. This active LOW signal, in conjunction with RD, is used to enable the output data three-state drivers and initiates a conversion if RD and HBEN are low. BUSY output indicates converter status. BUSY is LOW during conversion. Negative Supply, -12 V or -15 V. Positive Supply, +5 V.
PIN CONFIGURATION
0V TO 10V ANALOG INPUT -5V REFERENCE SOURCE C1
1
AIN VREFIN AGND D11 D10 D9 D8 D7 D6 D5 D4 DGND
VDD 24 VSS 23 BUSY 22 CS 21 RD 20
+5V -12V TO -15V STATUS OUTPUT P CONTROL INPUTS C3 XTAL C4
AIN VREFIN AGND D11 D10 D9 D8 D7 D6
C2 +
2 3 4 5 6 7 8 9 10 11 12
1 2 3 4 5 6
24 23
VDD VSS
ADC912A
22 BUSY 21 CS
HBEN 19 CLK OUT 18 CLK IN 17 D0/8 16 D1/9 15 D2/10 14 D3/11 13
ADC912A
20 RD
TOP VIEW 19 HBEN (Not to Scale) 18 CLK OUT 7
8 9 17 CLK IN 16 15 14 13
D0/8 D1/9 D2/10 D3/11
D5 10 D4 11 DGND 12
8-BIT OR 16-BIT P DATA BUS XTAL = 1MHz, C1 = 0.1 F, C3 = 10 F C3, C4 = 30pF TO 100pF DEPENDING ON XTAL CHOSEN
Figure 10. Basic Connection Diagram
-6-
REV. B
Typical Performance Characteristics-ADC912A
5
6 5 4
GAIN ERROR - LSB
INL-NONLINEARITY ERROR - LSB
0.4
4 3
OFFSET ERROR - LSB
0.2
2 1 0 -1 -2 -3
3 2 1 0 -1 -2 -3
0
-0.2
-0.4
-4
0 1024 2048 3072 4096
-5 -75
DIGITAL OUTPUT CODE
-50 -25 0 25 50 75 TEMPERATURE - C
100 125
-4 -75
0 25 50 75 -50 -25 TEMPERATURE - C
100 125
TPC 1. Nonlinearity Error vs. Digital Output Code
TPC 2. Offset Error vs. Temperature
TPC 3. Gain Error vs. Temperature
6 5 VDD @ 5.25V
80 DIGITAL OUTPUT CURRENT - mA PDISS = IDD 5 + ISS COUT = 20pF fCONV = 1/13 fCLK IN TA = 25 C EXT CLK IN 12
50 40 30 20 10 0 -10 -20 -30 -40 -50 1k 10k 100k 1M 0 1 2 3 4 5 CLK IN FREQUENCY - Hz VO OUTPUT VOLTAGE - Volts ISOURCE ISINK
SUPPLY CURRENT - mA
4 3 2 1 0 -1 -2 -3 -4 -75 ISS @ V SS = -15.75V CS, RD = LOGIC HIGH AIN = 10V CLK = 1MHz XTAL PDISS - mW 100 125
60
40
0
0 -50 -25 25 50 75 TEMPERATURE - C
TPC 4. Supply Current vs. Temperature
TPC 5. Power Dissipation vs. CLK IN Frequency
TPC 6. Digital Output Current vs. Output Voltage
256
NUMBER OF OCCURRENCES
192
90
LINEARITY ERROR - LSB
128
DIGITAL OUTPUT
256 SUCCESSIVE CONVERSIONS WITH AIN = 4.99756V
4
100
VDD = +5V VSS = -12V TA = 25 C
2
0
64
10 0%
-2
TRANSITION NOISE
0 2045 2046 2047 2048 2049 OUTPUT CODE - Decimal
-4 20 15 10 5 0
ANALOG INPUT
CONVERSION TIME - s
TPC 7. Code Repetition
TPC 8. Transition Noise Cross Plot
TPC 9. Linearity Error vs. Conversion Time
REV. B
-7-
ADC912A
CIRCUIT CHARACTERISTICS SYNCHRONIZING START CONVERSION
The characteristic curves provide more complete static and dynamic accuracy information necessary for repetitive sampling applications often used in DSP processing. One of the important characteristic curves provided displays integral nonlinearity error (INL) versus output code with a typical value of 1/4 LSB. Another very important characteristic associated with INL is the transition noise shown in the transition noise cross plot. The ADC912A offers extremely small, 1/6 LSB, transition noise which maintains the system signal-to-noise ratio in DSP processing applications. Code repetition plots show the precision internal comparator of the ADC912A making the same decision every time for dc input voltages. Code repetition along with no missing codes assures proper performance when the ADC912A is used in servo-control systems.
CONVERTER OPERATION DETAILS
Aligning the negative edge of RD with the rising edge of CLK IN provides synchronization of the internal start conversion signal to other system devices for sampling applications. When the negative edge of RD is aligned with the positive edge of CLK IN, the conversion will take 10.4 microseconds. The minimum setup time between the negative edge of CLK IN and the negative edge of RD is 180 ns. Without synchronization the conversion time will vary from 12.5 to 13.5 clock cycles. See Figure 12.
CS , RD
BUSY 180ns MIN CLK IN
The CS, RD, and HBEN digital inputs control the start of conversion. A high-to-low on both CS and RD initiate a conversion sequence. The HBEN high-byte-enable input must be low or coincident with the read RD input edge. The start of conversion resets the internal successive approximation register (SAR) and enables the three-state outputs. See Figure 11. The busy line is active low during the conversion process.
0V TO 10V AIN 5k
DB11 (MSB) BIT DECISION MADE
DB10
DB9
DB0
Figure 12. External Clock Input Synchronization
POWER ON INITIALIZATION
2.5k VREFIN - 0 TO + -VREF COMPARATOR
During system power-up the ADC912A comes up in a random state. Once the clock is operating or an external clock is applied, the first valid conversion begins with the application of a highto-low transition on both CS and RD. The next 13 negative clock edges complete the first conversion, producing valid data at the digital outputs. This is important in battery-operated systems where power supplies are shut down between measurement times.
DRIVING THE ANALOG INPUT
AGND 12 SAR
12-BIT LATCH
Figure 11. Simplified Analog Input Circuitry of ADC912A
During conversion, the SAR sequences the internal voltage output DAC from the most significant bit (MSB) to the least significant bit (LSB). The analog input connects to the comparator via a 5 k resistor. The DAC, which has a 2.5 k output resistance, connects to the same comparator input. The comparator, performing a zero crossing detection, tests the addition of successively weighted bits from the DAC output versus the analog input signal. The MSB decision occurs 200 ns after the second positive edge of the CLK IN following conversion initiation. The remaining 11-bit trials occur after the next 11 positive CLK IN edges. Once a conversion cycle is started it cannot be stopped or restarted, without upsetting the remaining bit decisions. Every conversion cycle must have 13 negative and positive CLK IN edges. At the end of conversion the comparator input voltage is zero. The SAR contains the 12-bit data word representing the analog input voltage. The BUSY line returns to logic high, signaling end of conversion. The SAR transfers the new data to the 12-bit latch.
During conversion, the internal DAC output current modulates the analog input current at the CLK IN frequency of 1.25 MHz. The analog input to the ADC912A must not change during the conversion process. This requires an external buffer with low output impedance at 1.25 MHz. Suitable devices meeting this requirement include the OP27, OP42, and the SMP-11.
CLK OUT
C1
ADC912A
* C2 CLK IN INTERNAL CLOCK 1M
*CRYSTAL OR CERAMIC RESONATOR
Figure 13. ADC912A Simplified Internal Clock Circuit
-8-
REV. B
ADC912A
INTERNAL CLOCK OSCILLATOR
4095
DIGITAL OUTPUT CODE - Decimal Equivalent
Figure 13 shows the ADC912A internal clock circuit. The clock oscillates at the external crystal or ceramic resonator frequency. The 1.25 MHz crystal or ceramic resonator connects between the CLK IN (Pin 17) and the CLK OUT (Pin 18). Capacitance values (C1, C2) depend on the crystal or ceramic resonator manufacturer. The crystal vendors should be qualified due to variations in C1 and C2 values required from vendor to vendor. Typical values range from 30 pF to 100 pF.
EXTERNAL CLOCK INPUT
4094
2 1
FULL-SCALE TRANSITION AT FS - 1.5 LSB
0 0.5 1
2
FS-2 FS-1 FS
A TTL compatible signal connected to CLK IN provides proper converter clock operation. No connection is necessary to the CLK OUT pin. The duty cycle of the external clock input can vary from 45% to 55%. Figure 12 shows the important waveforms.
EXTERNAL REFERENCE
AIN - ANALOG INPUT IN LSB
Figure 15. Ideal ADC912A Input/Output Transfer Characteristic
OFFSET AND FULL-SCALE ERROR ADJUSTMENT, UNIPOLAR OPERATION
A low output resistance, negative five volt reference is necessary. The external reference should be able to supply 3 mA of reference current. A bypass capacitor is necessary on the reference input lead to minimize system noise as the internal DAC switches. The reference input to the internal DAC is code dependent requiring anywhere from zero to 3 mA. The reference voltage tolerance has a direct influence on A/D converter full-scale voltage, and the maximum input full-scale voltage equals 2 x -VREF. The ADC912A is designed for ratiometric operation, but operation using reference voltages between -5.00 V and 0 V will result in degraded linearity performance. Integral linearity is fully tested and guaranteed for references of -5 V. Figure 14 provides a good -5 V reference that does not require precision resistors.
+5V TO +15V
For applications where absolute accuracy is important, offset and full-scale errors can be adjusted to zero. Figure 16 shows the extra components required for full-scale error adjustment. Zero offset is achieved by adjusting the null offset of the op amp driving AIN.
+12V VIN 0V TO 10V 3 2 4 7 A1 10k 1 -12V ZERO ADJUST FULL SCALE ADJUST 200 20k 6 5 10 1 AIN
ADC912A*
3
AGND
2 INPUT VOUT 6 REF02 TRIM GND 4 5 10k 100
0.01 F
+
10 F//0.01 F
2 3 OP77
A1: OP27 - LOWEST NOISE (TRIMMER CONNECTS BETWEEN PINS 1 & 8, WIPER TO 12V) OP42 - BEST BANDWIDTH *EXTRA PINS OMITTED FOR CLARITY
V+ V-
100 -5V OUTPUT
Figure 16. Unipolar 0 V to 10 V Operation
-12V TO -15V
TRIM IS OPTIONAL, ONLY NECESSARY FOR ABSOLUTE ACCURACY CIRCUITS
Figure 14. -5 V Reference
UNIPOLAR ANALOG INPUT OPERATION
Adjust the zero scale first by applying 1.22 mV (equivalent to 0.5 LSB input) to VIN. Adjust the op amp offset control until the digital output toggles between 0000 0000 0000 and 0000 0000 0001. The next step is adjustment of full scale. Apply 9.9963 V (equivalent to FS - 1.5 LSB) to VIN and adjust R1 until the digital output toggles between 1111 1111 1110 and 1111 1111 1111.
Figure 15 shows the ideal input/output characteristic for the 0 V to 10 V input range of the ADC912A. The designed output code transitions occur midway between successive integer LSB values (i.e., 0.5 LSB, 1.5 LSBs, 2.5 LSBs . . . FS - 1.5 LSBs). The output code is natural binary with 1 LSB = FS/4096 = (10/4096) V = 2.44 mV. The maximum full-scale input voltage is (10 x 4095/4096) V = 9.9976 V.
REV. B
-9-
ADC912A
BIPOLAR ANALOG INPUT OPERATION
Bipolar analog input operation is achieved with an external amplifier providing an analog offset. Figures 17 and 18 show two circuit topologies that result in different digital-output coding. In Figure 17, offset binary coding is produced when the external amplifier is connected in the inverting mode. Figure 19 shows the ideal transfer characteristics for both the inverting and noninverting configurations given in Figures 17 and 18.
VIN R3 RFS A1 R4 R2 RZ R1 -5V 0.1 F 10 F 3 AGND 2 VREFIN
Calibration of the bipolar analog input circuits (Figures 17 and 18) should begin with zero adjustment first. Apply a +1/2 LSB analog input to AIN, (see Tables II and III) and adjust RZ until the successive digital output codes flicker between the following codes: For noninverting, Figure 17 For inverting, Figure 18 1000 0000 0000 1000 0000 0001 0111 1111 1111 0111 1111 1110
1
AIN
Next, adjust full scale by applying a FS-3/2 LSB analog input to AIN, (see Tables II and III) and adjust RFS until the successive digital output codes flicker between the following codes: For Noninverting, Figure 17 1111 1111 1110 1111 1111 1111 For Inverting, Figure 18 0000 0000 0001 0000 0000 0000
Table II. Resistor and Potentiometer Values Required for Figure 17
ADC912A*
R1 = R2 = 20k SEE TABLE II FOR VALUES OF R3, R4, RZ, AND RFS A1: OP27 LOWEST NOISE, OP42 BEST BANDWIDTH *EXTRA PINS OMITTED FOR CLARITY
VIN Range
V 2.5 5.0 10.0
R3 k 0 20.0 29.8
R4 k 40.2 19.8 10.0
RZ k 0.5 0.5 0.5
RFS k 0.5 1.0 0.5
1/2 LSB mV 0.61 1.22 2.44
FS/2-3/2 LSB V 2.49817 4.99634 9.99268
Figure 17. Noninverting Bipolar Analog Input Operation
The scaling resistors chosen in bipolar input applications should be from the same manufacturer to obtain good resistor tracking performance over temperature. When potentiometers are used for absolute adjustment, 0.1% tolerance resistors should still be used as shown in Figures 17 and 18 to minimize temperature coefficient errors.
R2 RFS VIN R1 A1 RZ R3 -5V 1 AIN
Table III. Resistor and Potentiometer Values Required for Figure 18
VIN Range V 2.5 5.0 10.0 R1 k R2 k R3 k RZ k RFS k 1 1 1 1/2 LSB mV 0.61 1.22 2.44 FS/2-3/2 LSB V 2.49817 4.99634 9.99268
20.0 41.2 40.2 2 20.0 20.5 20.0 1 20.0 10.5 10.2 0.5
DIGITAL OUTPUT 111...111 111...110
ADC912A*
2V REFIN 0.1 F 10 F + 3 AGND
INVERTING FIGURE 18 NONINVERTING FIGURE 17 FS + 2 - 1LSB
SEE TABLE III FOR VALUES OF R1, R2, R3, R4, RZ, AND RFS A1: OP27 LOWEST NOISE, OP42 BEST BANDWIDTH *EXTRA PINS OMITTED FOR CLARITY
100...001 100...000 011...111
Figure 18. Inverting Bipolar Analog Input
011...110
000...001 000...000 FS -2 0V VIN - Input Voltage FS +2
Figure 19. Ideal Input/Output Transfer Characteristics for Bipolar Input Circuits
-10-
REV. B
ADC912A
MICROPROCESSOR INTERFACING
The ADC912A has self-contained logic for both 8-bit and 16-bit data bus interfacing. The output data can be formatted into either a 12-bit parallel word for a 16-bit data bus or an 8-bit data word pair for an 8-bit data bus. Data is always right justified, i.e., LSB is the most right-hand bit in a 16-bit word. For a two-byte read, only data outputs D7 . . . D0/8 are used. Byte selection is governed by the HBEN input which controls an internal digital multiplexer. This multiplexes the 12 bits of conversion data onto the lower D7 . . . D0/8 outputs (4 MSBs or 8 LSBs) where it can be read in two read cycles. The 4 MSBs always appear on D11 . . . D8 whenever the three-state output drivers are turned on. See Figure 20. Two A/D conversion modes of operation are available for both data bus sizes: the ROM mode and the Slow-Memory mode.
ADC912A
HBEN CS RD CLR "1" CONVERSION START (POSITIVE EDGE TRIGGER)
is correct, then the Slow-Memory mode is virtually immune to subsequent software modifications. Placing the microprocessor in the WAIT state has an additional advantage of quieting the digital system to reduce noise pickup in the analog conversion circuitry. The 12-bit parallel Slow-Memory mode provides the fastest analog sampling rate combined with digital data transfer rate for sampled-data systems.
PARALLEL READ, SLOW-MEMORY MODE (HBEN = LOW)
Figure 5 shows the timing diagram and data bus status for Parallel Read, Slow-Memory Mode. CS and RD going low triggers a conversion and the ADC912A acknowledges by taking BUSY low. Data from the previous conversion appears on the threestate data outputs. BUSY returns high at the end of conversion, when the output latches have been updated, and the conversion result is placed on data outputs D11 . . . D0/8.
TWO-BYTE READ, SLOW-MEMORY MODE
D
Q
BUSY ACTIVE HIGH (HBEN = "0")
ENABLE THREE-STATE OUTPUTS PINS: D11 ... D0/8 DATA BITS: DB11 ... DB0 ENABLE THREE-STATE OUTPUTS PINS: D11 ... D8 DATA BITS: DB11 ... DB8 PINS: D7 ... D4 DATA BITS: LOGIC LOW PINS: D3/11 ... D0/8 DATA BITS: DB11 ... DB8
For a two-byte read only the eight data outputs D7 . . . D0/8 are used. Conversion start procedure and data output status for the first read operation is identical to Parallel Read, Slow-Memory Mode. See Figure 6, Timing Diagram and Data Bus Status. At the end of conversion, the low data byte (DB7 . . . DB0) is read from the A/D converter. A second READ operation with HBEN high places the high byte on data outputs D3/11 . . . D0/8 and disables conversion start. Note the 4 MSBs also appear on data outputs D11 . . . D8 during these two READ operations.
PARALLEL READ, ROM MODE (HBEN = LOW)
ACTIVE HIGH (HBEN = "1")
Figure 20. Internal Logic for Control Inputs CS, RD, and HBEN
In the ROM mode each READ instruction obtains new, valid data, assuming the minimum timing requirements are satisfied. However, since the data output from a current READ instruction was generated from a conversion initiated by a previous READ operation, the current data may be out-of-date. To be sure of obtaining up-to-date data, READ instructions may be coded in pairs (with some NOPs between them); use only the data from the second READ in each pair. The first READ starts the conversion, the second READ gets the results. The Slow-Memory mode is the simplest. It is the method of choice where compact coding is essential, or where software bugs are a hazard. In this mode, a single READ instruction will initiate a data conversion, interrupt the microprocessor until completion (WAIT states are introduced), then read the results. If the system throughput tolerates WAIT states, and the hardware
A conversion is started with a READ operation. The 12 bits of data from the previous conversion are available on data outputs D11 . . . D0/8 (see Figure 7). This data may be disregarded if not required. A second READ operation reads the new data (DB11 . . . DB0) and starts another conversion. A delay at least as long as the ADC912A conversion time must be allowed between READ operations. If a READ takes place prior to the end of 13 CLKS of the ADC conversion, the remaining bits not yet tested will be invalid.
TWO-BYTE READ, ROM MODE
For a two-byte read only the data outputs D7 . . . D0/8 are used. Conversion is started in the same way with a READ operation and the data output status is the same as the Parallel Read, ROM Mode. See Figure 8, Two-Byte Read Timing Diagram, ROM Mode. Two more READ operations are required to obtain the new conversion result. A delay equal to the ADC912A conversion time must be allowed between conversion start and places the high byte (4 MSBs) on data outputs D3/11 . . . D0/8. A third READ operation accesses the low data byte (DB7 . . . DB0) and starts another conversion. The 4 MSBs also appear on data outputs D11 . . . D8 during all three read operations above.
REV. B
-11-
ADC912A
CIRCUIT LAYOUT GUIDELINES INTERFACING TO THE TMS32010 DSP PROCESSOR
As with any high-speed A/D converters, good circuit layout practice is essential. Wire-wrap boards are not recommended due to stray pickup of the high-frequency digital noise. A PC board offers the best results. Digital and analog grounds should be separated even if they are ground planes instead of ground traces. Do not lay digital traces adjacent to highimpedance analog traces. Avoid digital layouts that radiate high-frequency clock signals; i.e., do not lay out digital signal lines and ground returns in the shape of a loop antenna. Shield the analog input if it comes from a different PC board source. Set up a single point ground at AGND (Pin 3) of the ADC912A; tie all other analog grounds to this point. Also tie the logic power supply ground, but no other digital grounds, to this point (see Figure 21). Low impedance analog and digital power supply common returns are essential to low noise operation of the ADC. Their trace widths should be as wide as possible. Good power supply bypass capacitors located near the ADC package ensure quiet operation. Place a 10 F capacitor in parallel with a 0.01 F ceramic capacitor across VDD to ground and VSS to ground (near Pin 3).
Figure 22 shows an ADC912A to TMS32010 interface. The ADC912A is operating in the ROM mode. The interface is designed for the maximum TMS32010 clock frequency of 20 MHz.
ADDRESS BUS PA0 CS RD ADDRESS DECODE EN DEN PA2
ADC912A*
D11 D0/8 HBEN
TMS32010*
DATA BUS
D15 D0
*ESSENTIAL INTERFACE CIRCUITRY SHOWN FOR CLARITY
Figure 22. ADC912A to TMS32010 DSP Processor Interface
ANALOG SUPPLY +15V GND -15V +5V
DIGITAL SUPPLY RETURN
The ADC912A is mapped at a user-selected port address (PA). The following I/O instruction starts a conversion and reads the previous conversion into the data memory: IN DATA, PA PA = Port Address DATA = Data Memory Location
COMMON GROUND
When conversion is complete, a second I/O instruction reads the new data into the data memory and starts another conversion. Sufficient A/D conversion time must be allowed between I/O instructions. The very first data read after system power-up should be discarded.
AGND VSS DGND VDD ADC912A DIGITAL CIRCUITS
ANALOG CIRCUITS
USING WAIT STATES
Figure 21. Power Supply Grounding
In applications where the ADC912A data outputs and control signals are connected to a continuously active microprocessor bus, it is possible to get LSB level errors in conversion results. These errors are due to a feedthrough from the microprocessor to the internal comparator. The problem can be minimized by forcing the microprocessor into a WAIT state during conversion (see Slow-Memory microprocessor interfacing). An alternate method is isolation of the data bus with three-state buffers, such as the 74HC541.
The TMS32020 DSP processor has the added capability of WAIT states. This feature simplifies the hardware required for slow memory devices by extending the microprocessor bus access time. Figure 23 shows an ADC912A to TMS32020 interface using one WAIT state to guarantee data interface at the full 20 MHz clock frequency. This WAIT state extends the bus access time by 200 ns. In this circuit the ADC912A operated in the ROM mode where each input instruction (IN DATA, PA) takes the previous conversion result and stores it in memory. The next input instruction must be delayed for the length of the A/D conversion time so that a new conversion result can be read.
-12-
REV. B
ADC912A
SLOW-MEMORY MODE OPERATION USING WAIT STATES
ADDRESS BUS A0 ADDRESS DECODE RD CS "1" D 7474 Q 20MHz EN IS A15
The WAIT state feature of the TMS32020 can also be used to operate the ADC912A in the Slow-Memory mode. This is accomplished by driving the clock input of the 7474 flip-flop in Figure 23, from the BUSY output of the ADC912A, instead of the CLK OUT 1 of the TMS32020. Once a conversion has started the READY input of the TMS32020 is not released until the ADC912A completes its 12-bit A/D conversion. This stops the TMS32020 during the conversion process reducing microprocessor system noise generation. Another advantage for the system software is the single instruction IN MEM, PA used to start, process, and read the results of the A/D conversion. This makes the software code more transportable between systems operating at different clock speeds. The disadvantage is some loss in instruction processing time.
R/W READY TMS32020 2/CLK IN CLK OUT1 D15 D0
ADC912A*
BUSY D11 D0/8 HBEN
CLR CK
SLOW-MEMORY MODE
ROM MODE (ONE WAIT STATE)
DATA BUS
*ESSENTIAL INTERFACE CIRCUITRY SHOWN FOR CLARITY
Figure 23. ADC912A to TMS32020 Interface Using Wait States
REV. B
-13-
ADC912A
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
24-Lead Narrow Body Plastic DIP Package (N-24)
1.275 (32.30) 1.125 (28.60)
24 1 13 12
0.280 (7.11) 0.240 (6.10) 0.325 (8.25) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93) 0.015 (0.381) 0.008 (0.204)
PIN 1 0.210 (5.33) MAX 0.200 (5.05) 0.125 (3.18) 0.022 (0.558) 0.014 (0.356) 0.060 (1.52) 0.015 (0.38) 0.150 (3.81) MIN 0.100 (2.54) BSC 0.070 (1.77) SEATING 0.045 (1.15) PLANE
24-Lead Wide Body SOIC Package (R-24)
0.6141 (15.60) 0.5985 (15.20)
24
13
0.2992 (7.60) 0.2914 (7.40)
1 12
0.4193 (10.65) 0.3937 (10.00)
PIN 1
0.1043 (2.65) 0.0926 (2.35)
0.0291 (0.74) 0.0098 (0.25)
45
0.0118 (0.30) 0.0500 0.0040 (0.10) (1.27) BSC
8 0 0.0192 (0.49) SEATING 0.0125 (0.32) PLANE 0.0138 (0.35) 0.0091 (0.23)
0.0500 (1.27) 0.0157 (0.40)
-14-
REV. B
Revision History-ADC912A
Location Page
Data Sheet changed from REV. A to REV. B. Changes to General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Changes to Static Accuracy section of Specification page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Edits to Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Edits to Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Changes to Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
REV. B
-15-
-16-
C00384-0-6/01(B)
PRINTED IN U.S.A.

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